PCI configuration registers:
  Common header:
    0x00: 0x036910de 0x00b00106 0x050000a2 0x00000000

    Vendor Name: NVIDIA (0x10de)
    Device Name: nForce MCP55 Memory Controller (0x0369)
    Command register: 0x0106
      I/O space accesses: off
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): on
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x00b0
      Capability List support: on
      66 MHz capable: on
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: fast (0x0)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: memory (0x05)
    Subclass Name: RAM (0x00)
    Interface: 0x00
    Revision ID: 0xa2
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x00
    Cache Line Size: 0x00

  Type 0 ("normal" device) header:
    0x10: 0x00000000 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x1714103c
    0x30: 0x00000000 0x00000044 0x00000000 0x000000ff

    Base address register at 0x10
      not implemented(?)
    Base address register at 0x14
      not implemented(?)
    Base address register at 0x18
      not implemented(?)
    Base address register at 0x1c
      not implemented(?)
    Base address register at 0x20
      not implemented(?)
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x103c
    Subsystem ID: 0x1714
    Expansion ROM Base Address: 0x00000000
    Capability list pointer: 0x44
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x00 (none)
    Interrupt line: 0xff

  Capability register at 0x44
    type: 0x08 (LDT)
  Capability register at 0xdc
    type: 0x08 (LDT)

  Device-dependent header:
    0x40: 0x1714103c 0x01e0dc08 0x11112022 0x000000d0
    0x50: 0x007f0523 0x00000003 0x00030000 0x00000000
    0x60: 0x00000000 0x00000000 0x00000000 0x000a3606
    0x70: 0x00444444 0x000009d0 0x00000011 0x00881111
    0x80: 0x00889923 0x0e6400fa 0x00000002 0x0000007f
    0x90: 0x80000070 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x01010101 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x0f0f0080
    0xd0: 0x00000000 0x00000000 0x00000000 0xa8010008
    0xe0: 0xfee00000 0x00000000 0x00800000 0x00d0fff0
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000